verilog HDLBits刷题[Finite State Machines]“Fsm1”---Simple FSM1(synchronous reset)
1、题目
This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
This exercise is the same as fsm1, but using synchronous reset. 2、代码
// Note the Verilog-1995 module dec…