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System Verilog浅学——7.typedef——union

2026/9/24 23:15:28 拓冰建站 浏览量
System Verilog浅学——7.typedef——union

Union

联合类型的语法:

typedef union packed{struct packed{logic zero;logic [31:0]aluout;} alu;struct packed{logic zero;logic [31:0] pcbranch;}branch;struct packed {logic [31:0] addr;logic mem_read;}memory;
} result_t;result_t res;logic [31:0]addr, aluout;
assign addr = res.memory.addr; //assign addr = res[32:1]
assign aluout = res.alu.aluout;//assign aluout = res[31:0]

对union类型的变量进行赋值时,要注意多驱动
‘0是位全0,'1是位全1