xsct xsdb 调试寄存器

提示符 xsdb xsct 通用；

老版本的vivado vitis 可能没有

****** Xilinx Software Commandline Tool (XSCT) v2022.1.0**** SW Build 303 on 2022-04-13-17:42:48** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.xsct% cd {C:\work_folder\case\case00441451}
xsct% pwd
C:/work_folder/case/case00441451
xsct% ls
WARNING: [Common 17-259] Unknown Tcl command 'ls' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
design_1_wrapper.pdi
xsct% connect
attempting to launch hw_server****** Xilinx hw_server v2022.1**** Build date : Apr 18 2022 at 16:02:36** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application****** Xilinx hw_server v2022.1**** Build date : Apr 18 2022 at 16:02:36** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.INFO: hw_server application startedINFO: Use Ctrl-C to exit hw_server applicationINFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121tcfchan#0
xsct% ta1  Versal xcvc19022  RPU (PS POR is active)3  Cortex-R5 #0 (PS POR is active)4  Cortex-R5 #1 (PS POR is active)5  APU (FPD domain isolation)6  Cortex-A72 #0 (FPD domain isolation)7  Cortex-A72 #1 (FPD domain isolation)8  PPU9  MicroBlaze PPU (Sleeping after reset)10  PSM11  PMC12  PL13  DPC
xsct% ta 1
xsct% ta1* Versal xcvc19022  RPU (PS POR is active)3  Cortex-R5 #0 (PS POR is active)4  Cortex-R5 #1 (PS POR is active)5  APU (FPD domain isolation)6  Cortex-A72 #0 (FPD domain isolation)7  Cortex-A72 #1 (FPD domain isolation)8  PPU9  MicroBlaze PPU (Sleeping after reset)10  PSM11  PMC12  PL13  DPC
xsct% device program design_1_wrapper.pdi
100%    1MB   1.4MB/s  00:01
xsct% ta1* Versal xcvc19022  RPU (Reset)3  Cortex-R5 #0 (RPU PGE Reset)4  Cortex-R5 #1 (RPU PGE Reset)5  APU6  Cortex-A72 #0 (Power On Reset)7  Cortex-A72 #1 (Power On Reset)8  PPU9  MicroBlaze PPU (Sleeping)10  PSM14  MicroBlaze PSM (Sleeping)11  PMC12  PL13  DPC
xsct% ta 6
xsct% ta1  Versal xcvc19022  RPU (Reset)3  Cortex-R5 #0 (RPU PGE Reset)4  Cortex-R5 #1 (RPU PGE Reset)5  APU6* Cortex-A72 #0 (Power On Reset)7  Cortex-A72 #1 (Power On Reset)8  PPU9  MicroBlaze PPU (Sleeping)10  PSM14  MicroBlaze PSM (Sleeping)11  PMC12  PL13  DPC
xsct% rst -processor
WARNING: If the reset is being triggered after powering on the device,write bootloop at reset vector address (0xffff0000), or use-clear-registers option, to avoid unpredictable behavior.Further warnings will be suppressed
WARNING: Default system will be activated before triggering reset.Use skip-activate-subsystem to skip this.Further warnings will be suppressed
Info: Cortex-A72 #0 (target 6) Stopped at 0xffff0000 (Reset Catch)
xsct% ta1  Versal xcvc19022  RPU3  Cortex-R5 #0 (Halted)4  Cortex-R5 #1 (Lock Step Mode)5  APU6* Cortex-A72 #0 (Reset Catch, EL3(S)/A64)7  Cortex-A72 #1 (Power On Reset)8  PPU9  MicroBlaze PPU (Sleeping)10  PSM14  MicroBlaze PSM (Sleeping)11  PMC12  PL13  DPC
xsct% mwr -force 0x20100000000 0x12345678
xsct% mrd -force 0x2010000000020100000000:   12345678xsct%